What you’d need on the bench
A Digilent Basys 3 board built around a Xilinx Artix-7, an OV7670 camera module wired straight into the Pmod pins, a VGA monitor, and a Vivado install. That’s the whole shopping list for Zakriya Paracha’s handwritten-digit recognizer. There is no Raspberry Pi in the middle, no Arduino babysitting the camera, and no USB bridge. Once the bitstream is loaded, nothing in the system is executing instructions at all.
Most “AI on hardware” builds quietly keep a processor around. Something has to boot, load weights into RAM, and call an inference library. Paracha removed that layer completely. He trained a small feed-forward network in PyTorch on the MNIST dataset, then rebuilt the trained network as Verilog. The multiply-accumulate steps, the memory reads, the argmax at the end: all of it became dedicated circuits. The FPGA is not accelerating the neural network. It is the neural network.
How the numbers were squeezed down
The model takes a 28×28 image, runs it through a hidden layer of 32 neurons, and outputs probabilities for ten digits. That comes to 25,888 weights. Stored as floats, they would swallow more Block RAM than the Artix-7 has to give, so every weight was quantized to an 8-bit integer. Model size fell from roughly 98 KB to 25 KB and recognition accuracy dropped by 0.18%, which is a rounding error next to what you get back in memory.
The image pipeline is the part worth studying. Video streams in from the OV7670, and hardware blocks grab each frame, convert it to grayscale, crop the center, downsample to 28×28, then threshold it so the input resembles the training images. A finite state machine walks the multiply-accumulate loop. One tidy trick: dividing by 1024 is done as a right-shift of ten bits, so no divider circuit is needed at all. Total inference time is about half a millisecond, and the board simultaneously drives a VGA display showing each stage while the seven-segment readout prints the predicted digit and its confidence.
Worth building, with one caveat
FPGAs will not displace GPUs for general machine learning. Models change weekly, and resynthesizing logic for every retrain is a bad trade. For a small fixed network where latency has to be deterministic, though, this approach is hard to beat. For an ECE student, it also collapses digital design, quantization, and computer vision into a single project you can point at during a thesis defense. Read Paracha’s full write-up on Hackster, then start with the camera-to-VGA passthrough on its own before you add a single neuron.
Frequently Asked Questions
What hardware does this digit recognizer actually run on?
A Digilent Basys 3 board with a Xilinx Artix-7 FPGA, plus an OV7670 camera wired directly to the Pmod pins and a VGA monitor for the visualization. No microcontroller or single-board computer sits anywhere in the chain.
Why quantize the weights to 8-bit integers?
The trained network holds 25,888 weights. As floating-point values they would not fit in the Artix-7’s Block RAM. Dropping to 8-bit integers cut the model from about 98 KB to 25 KB and cost only 0.18% recognition accuracy.
What will I learn if I build this?
You practice Verilog RTL design, finite state machines, and fixed-point quantization, plus the camera interfacing and VGA timing that most digital design courses only cover on paper. It also teaches you to reason about latency in clock cycles rather than milliseconds, which is the mindset embedded and hardware roles look for.
